1. Field of the Invention
The present invention relates to a communication apparatus applying a frequency synthesizer wherein a direct digital synthesizer is used. Particularly, this invention relates to downsizing and a high precision receiving/transmitting apparatus and a frequency synthesizer used in radio communications systems.
2. Description of the Related Art
FIG. 48 shows an example configuration of a conventional receiving apparatus constructed based on a receiving apparatus including an auto frequency control (AFC) circuit. The receiving apparatus including the auto frequency control circuit is disclosed in "TDMA Communication" by Heiichi Yamamoto et al Institute of Electronics and Communication pp. 87-89, Spring Conference B-198 of Electronics Information Communication Institute in 1993, Unexamined Japanese Patent Publication 3-284016, Unexamined Japanese Patent Publication 3-296318, and Unexamined Japanese Patent Publication 4-156712.
In FIG. 48, a low noise amplifier (LNA) 1, band pass filters (BPF) 2a, 2b and 2c, mixers (MIX) 3a and 3b, a phase locked loop (PLL) synthesizer 4, a temperature compensation quartz-crystal oscillator (TCXO) 5, a frequency converter 6 for high frequency, amplifiers (AMP) 7a and 7b, a voltage-controlled quartz-crystal oscillator (VCXO) 8, a frequency converter 9 for low frequency, an analog-digital converter (A-D converter) 10, a frequency error detecting means 11, a frequency control means 12, a memory 13, and a digital-analog converter (D-A converter) 14 are provided. The frequency converter 6 for high frequency includes the LNA 1, the BPF 2a, the MIX 3a, the TCXO 5 and the PLL synthesizer 4. An output frequency of the PLL synthesizer 4 is controlled based on channel setting data. A receiving frequency is set based on the controlled output frequency from the PLL synthesizer 4. The frequency converter 9 for low frequency includes the AMP 7a, the BPF 2b, the MIX 3b and the VCXO 8. The receiving frequency can be adjusted finely based on a control voltage applied at the VCXO 8.
The operation will now be described. In the conventional receiving apparatus shown in FIG. 48, a frequency of an input signal is changed to an intermediate frequency (IF) signal of a predetermined frequency through the frequency converter 6 for high frequency and the frequency converter 9 for low frequency. The changed frequency is amplified at the AMP 7b and filtered at the BPF 2c. By this procedure, other input signals of neighboring frequencies are suppressed. The filtered frequency is converted from analog to digital at the A-D converter 10. In a common receiving apparatus for digital communication, an input signal expressed in digital amount is demodulated by digital operation and a transmission signal is extracted. In this case, there is a difference between a center frequency of the input signal and a receiving frequency in the receiving apparatus. This frequency difference is hereinafter called a frequency error. If the frequency error increases, the modulation performance (bit error rate in a digital transmission method) is gradually deteriorated. If the frequency error increases too far, it becomes impossible to receive the input signal because the input signal is defined to be out of passing bandwidth of the BPF 2c. The phenomenon, such as the above, becomes distinctive especially in a slow transmission speed system, such as a single channel per carrier (SCPC) method wherein speech transmission is mainly treated.
Generally, in the receiving apparatus as shown in FIG. 48, the frequency error is detected by the frequency error detecting means 11, a frequency of the VCXO 8 is controlled, and the frequency error is corrected in addition to the modulation operation. Based on frequency error data obtained by the frequency error detecting means 11, frequency control data is calculated for the purpose of correcting the frequency error in the receiving frequency by the frequency control means 12. The memory 13 is accessed based on the frequency control data. A table for output frequency of the VCXO 8 vs. control voltage, or a table for increased amount of the output frequency of the VCXO 8 vs. increased amount of the control voltage is stored in this memory 13. Voltage data applied at the VCXO 8 is output from the memory 13 based on the frequency control data. The voltage data is converted to the control voltage for the VCXO 8 at the D-A converter 14. The above serial controlling of the frequency is called AFC. (auto frequency control)
FIG. 49 shows a configuration of the PLL synthesizer 4. A variable divider 15, a reference signal divider 16, a phase comparator 17, a loop filter 18, a voltage-controlled oscillator (VC0) 19, the temperature compensation quartz-crystal oscillator (TCXO) 5 and a PLL 34 are shown in FIG. 49. The temperature compensation quartz-crystal oscillator (TCXO) 5 is a reference oscillator. A frequency of output signal of the VC0 19 is divided by dividing ratio N in the variable divider 15. A frequency of output signal of TCXO 5 is divided by dividing ratio R in the reference signal divider 16. The PLL operates in order to make the above divided frequencies be coincident. Accordingly, output frequency fout of the PLL 34 is N/R times output frequency fxo of TCXO 5 (fout=(N/R).multidot.fxo). The output frequency fout of the PLL synthesizer 4 can be switched by interval fxo/R. The output frequency fout can be switched by changing dividing ratio N of the variable divider 15. The dividing ratio N is changed by the channel setting data.
Other configurations of the PLL synthesizer 4 are shown in FIG. 50 and U.S. Pat. No. 4,965,533. The configuration of FIG. 50 is described in the paper, A. L. Bramble, "Direct Digital Frequency Synthesis", IEEE 35th Ann. Frequency Control Symposium, May 1981, pp. 406-414.
In FIG. 50, a direct digital synthesizer (DDS) 31, a reference clock 32 and a frequency divider 33 are shown. The DDS 31 synchronized with the reference clock 32 is used as a reference oscillator of PLL 34, in this PLL synthesizer 4.
FIG. 51 shows a configuration of the DDS 31. A phase accumulator 40, a memory 41, a digital-analog converter 42 and a filter 43 are shown in FIG. 51. Frequency data (.DELTA..phi.) represented by plural bits is input and accumulated at the phase accumulator 40 in the DDS 31. The accumulated data is converted to phase data .phi. and output. Amplitude data sin .phi. of a sine wave is stored in the memory 41 in advance. The amplitude data sin .phi. of a sine wave is output based on the phase data .phi.. The output data is converted to analog waveform at the D-A converter 42. The above digital operation is performed synchronous with the reference clock. Output from the D-A converter 42 is input into the filter 43. Spurious components of the reference clock, higher harmonic and so forth is removed at the filter 43. High-frequency resolution can be easily obtained by increasing the number of bits of the frequency data (.DELTA..phi.), without deteriorating other characteristics, in DDS 31. Accordingly, high-frequency resolution also can be obtained in the PLL 34 whose reference oscillator is the DDS 31.
FIG. 52 shows another configuration of the DDS 31. In this DDS 31, a sin .phi. operation circuit 44 is provided instead of the memory 41. The sin .phi. calculation circuit 44 is provided in order to avoid making the capacity of the memory 41 large when the high-frequency resolution is obtained by increasing the number of bits of the frequency data (.DELTA..phi.)in the DDS 31. CORDIC algorithm and so forth is used in the sin .phi. calculation circuit 44. The amplitude data sin .phi. of a sine wave is obtained by digital operation.
There are many disadvantages to the conventional receiving apparatus. For example, when a narrow bandwidth digital transmission of low symbol speed is performed for transmitting speech in SCPC (single channel per carrier), it is necessary to enhance the frequency setting accuracy at AFC. The reason is that the BPF 2c becomes a narrow band. The receiving frequency is finely adjusted by treating the frequency control data through the D-A converter 14, the memory 13 and the VCXO 8, in the conventional receiving apparatus. The VCXO 8 has a configuration wherein a varactor diode is connected to a quartz-crystal resonator for modulating the frequency. Thus sensitivity of the modulation is changed depending upon control voltage. Therefore, in order to enhance the frequency setting accuracy, it is needed to increase the number of entries for a table of output frequency vs. control voltage stored in the memory 13 for enhancing the resolution. This increase introduces a problem of a larger memory 13 requirement.
In addition, an output frequency of the VCXO 8 and the modulation sensitivity of the VCXO 8 are changed depending upon temperature. Therefore, it has another problem that the frequency setting accuracy is deteriorated with temperature variations.
Moreover, characteristics of the VCXO 8 relating to output frequency vs. control voltage differs depending upon each VCXO. In order to set the frequency highly accurately, it is necessary to measure the characteristic data of output frequency vs. control voltage for each receiving apparatus and to write the data into the memory 13. This rewriting procedure introduces another problem of higher cost.
As one of solutions for the above problems relating to the AFC, the following method is introduced. A digital oscillator is described in the book, "Digital Movement Communication", edited by Syuji Kuwahara, Kagaku Syuppan, pp. 269-271. The method for the solution is to correct a frequency error by a digital operation using the digital oscillator. FIG. 53 shows a configuration of the method.
A demodulator 35 and a digital oscillator 36 are shown in FIG. 53. It is easy to enhance the frequency setting accuracy according to this configuration. However, this method can not be applied when the frequency error is large and thus when an input signal is out of the passing bandwidth of the BPF 2c.
Problems in applying the VCXO 8 to the AFC in the receiving apparatus have been described. A similar configuration is also used for a transmitting apparatus in order to control a transmitting frequency. Namely, a transmitting frequency error is calculated based on a receiving frequency error. The VCXO 8 used as a local oscillator for the transmitting apparatus is controlled depending upon the transmitting frequency error. In this case also, there is the problem that the amount of the memory 13 becomes large in enhancing the frequency setting accuracy because the VCXO 8 is used. There is also the problem that a desired frequency setting accuracy can lead to high cost.
Now, the problem of the conventional PLL synthesizer shown in FIG. 49 when being applied in the receiving apparatus will be described.
Generally, phase comparison frequency fr (fr=fxo/R) of the PLL synthesizer wherein a frequency is switched by a variable divider is the same as a channel frequency interval. Therefore, the phase comparison frequency fr of the PLL synthesizer becomes low frequency in a system wherein the frequency interval of the channel is narrow, such as SCPC method of low transmission speed. In this case, phase noise PN close to a carrier wave of the PLL synthesizer increases, which brings about a problem that communication quality and selecting receiving frequency accuracy are deteriorated. The phase noise PN close to the carrier wave of the PLL synthesizer can be obtained in the following equation. EQU PN=10.multidot.LOG.sub.10 {(fout/fr).sup.2 .multidot.(1/2).multidot.(Ef/Kp).sup.2 }(dBc/Hz) (1)
In the equation, fout is output frequency of the PLL 34, Ef is noise voltage for input conversion for the loop filter and, Kp is signal detection sensitivity of the phase comparator 17. When the phase comparison frequency fr becomes low frequency, loop bandwidth of the PLL 34 also becomes narrow. Therefore, response speed of the PLL 34 becomes slow, which brings about a problem that the frequency switching time becomes long.
The PLL synthesizer 4 wherein the DDS 31 is used as a reference oscillator of the PLL 34, shown in FIG. 50, has been introduced to improve the above disadvantages. The variable divider 15 is not used in this PLL synthesizer 4 because the frequency is changed by the DDS 31. Therefore, it is possible to optionally select the phase comparison frequency fr. In addition, since a frequency is changed by the DDS 31, a frequency of narrow channel can be easily obtained without deteriorating the characteristics relating to the phase noise and the frequency switching time and so forth. Namely, the problems of increasing phase noise and lengthening frequency switching time can be solved. However, there is a problem that spurious components caused by a quantization error is high because the DDS 31 generates a sine wave by digital operation.
FIG. 54 shows an example of an output spectrum of the DDS 31. The spurious component is amplified in the passing bandwidth in the PLL 34. Assuming that the spurious component of the DDS 31 is SPdds (dBc) and the spurious component of the output signal from the PLL synthesizer 4 is SPout (dBc), the relation between these two can be obtained in the following equation. EQU SPout=10.multidot.LOG.sub.10 (fout/fr).sup.2 +SPdds=10.multidot.LOG.sub.10 (N).sup.2 +SPdds(dBc) (2)
The spurious component in such a configuration of the PLL synthesizer is high, which brings about a problem that the communication quality and the frequency selecting accuracy are deteriorated. Therefore, the output frequency fout applied to such PLL synthesizer is relatively restricted to be a low frequency.
Though there is a method of increasing the output frequency (phase comparison frequency) fr of the DDS 31 in order to solve the above problems, this method has another problem. The problem is that electrical power consumption increases in proportion to an operating frequency as shown in FIG. 55.